DDR SDRAMDDR SDRAM

 

 

64Mb DDR SDRAM
Data Sheet Micron Parts
64Mb: x32 DDR SDRAM MT46V2M32

128Mb DDR SDRAM
Data Sheet Micron Parts
128Mb: x32 DDR SDRAM MT46V4M32
128Mb: x4, x8, x16 DDR SDRAM MT46V16M8
MT46V32M4
MT46V8M16

256Mb DDR SDRAM
Data Sheet Micron Parts
256Mb: x4, x8, x16 DDR SDRAM MT46V16M16
MT46V16M16D1
MT46V16M16D2
MT46V32M8
MT46V64M4

DDR SDRAM (Advance Information)
Data Sheet  
256Mb: x4, x8, x16 DDR333 SDRAM Addendum MT46V64M4
MT46V32M8
MT46V16M16
512Mb: x4, x8, x16 DDR SDRAM MT46V128M4,
MT46V64M8,
MT46V32M16

 

64Mb: x32 DDR SDRAM

 Part Features

  • Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture
  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
  • Reduced output drive option
  • Differential clock inputs (CK and CK#)
  • Commands entered on each positive CK edge
  • DQS edge-aligned with data for READs; center-aligned with data for WRITEs
  • DLL to align DQ and DQS transitions with CK
  • Four internal banks for concurrent operation
  • Data mask (DM) for masking write data
  • Programmable burst lengths: 2, 4, 8, or full page
  • 32ms, 4,096-cycle auto refresh (7.8µs/cycle)
  • Auto precharge option
  • Auto Refresh and Self Refresh Modes
  • Programmable I/O (SSTL_2 compatible) – reduced and impedance matched

Part Options

Options Marking Notes
Configuration    
2 Meg x 32 2M32 512K x 32 x 4 banks
Power Supply    
2.5V VDD/VDDQ V1  
2.65V VDD/VDDQ none  
Plastic Package (OCPL)    
100-pin TQFP LG  0.65mm lead pitch
Timing (Cycle Time)    
200 MHz @ CL = 3 -5  
183 MHz @ CL = 3 -55  
166 MHz @ CL = 3 -6
 
150 MHz @ CL = 3 -65
 

 

128Mb: x32 DDR SDRAM

 Part Features

  • VDD = +2.5V ±0.125V, VDDQ = +2.5V ±0.125V
  • Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture
  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
  • Reduced output drive option
  • Differential clock inputs (CK and CK#)
  • Commands entered on each positive CK edge
  • DQS edge-aligned with data for READs; center-aligned with data for WRITEs
  • DLL to align DQ and DQS transitions with CK
  • Four internal banks for concurrent operation
  • Data mask (DM) for masking write data
  • Programmable burst lengths: 2, 4, 8, or full page
  • 32ms, 4,096-cycle auto refresh
  • Auto precharge option
  • Auto Refresh and Self Refresh Modes
  • 2.5V I/O (SSTL_2 compatible)
  • DQS per byte on the FBGA package
  • 1.8V VDDQ for FBGA package
  • tRAS lockout

Part Options

Options Marking Notes
Configuration    
4 Meg x 32 2M32 1 Meg x 32 x 4 banks 
Plastic Package (OCPL)    
100-pin TQFP LG   0.65mm lead pitch
12mm x 12mm FBGA FK  
Timing (Cycle Time)    
250 MHz @ CL = 4 -4  
222 MHz @ CL = 4 -45  
200 MHz @ CL = 3 -5  
Self Refresh    
Standard none  

 

128Mb: x4, x8, x16 DDR SDRAM

Part Features

  • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
  • Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte)
  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
  • Differential clock inputs (CK and CK#)
  • Commands entered on each positive CK edge
  • DQS edge-aligned with data for READs; center-aligned with data for WRITEs
  • DLL to align DQ and DQS transitions with CK
  • Four internal banks for concurrent operation
  • Data mask (DM) for masking write data (x16 has two – one per byte)
  • x16 has programmable IOL/IOH option
  • Programmable burst lengths: 2, 4, or 8
  • Auto precharge option
  • Auto Refresh and Self Refresh Modes
  • Longer lead TSOP for improved reliability (OCPL)
  • 2.5V I/O (SSTL_2 compatible)

Part Options

Options Marking Notes
Configurations    
32 Meg x 4 32M4 8 Meg x 4 x 4 banks  
16 Meg x 8 16M8 4 Meg x 8 x 4 banks  
8 Meg x 16  8M16 2 Meg x 16 x 4 banks 
Plastic Package (OCPL)    
66-pin TSOP TG 400 mil width, 0.65mm pin pitch
Timing (Cycle Time)    
7.5ns @ CL = 2 (DDR266B) -75Z Supports PC2100 modules with 2-3-3 timing
7.5ns @ CL = 2.5 (DDR266B) -75 Supports PC2100 modules with 2.5-3-3 timing
10ns @ CL = 2 (DDR200) -8 Supports PC1600 modules with 2-2-2 timing
Self Refresh    
Standard None  
Low-Power L  

 

256Mb: x4, x8, x16 DDR SDRAM

Part Features

  • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
  • Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte)
  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
  • Differential clock inputs (CK and CK#)
  • Commands entered on each positive CK edge
  • DQS edge-aligned with data for READs; center-aligned with data for WRITEs
  • DLL to align DQ and DQS transitions with CK
  • Four internal banks for concurrent operation
  • Data mask (DM) for masking write data (x16 has two – one per byte)
  • Programmable burst lengths: 2, 4, or 8
  • Auto Refresh and Self Refresh Modes
  • Longer lead TSOP for improved reliability (OCPL)
  • 2.5V I/O (SSTL_2 compatible)
  • Concurrent auto precharge option is supported

Part Options

Options Marking Notes
Configurations    
64 Meg x 4 64M4 16 Meg x 4 x 4 banks
32 Meg x 8 32M8 8 Meg x 8 x 4 banks
16 Meg x 16  16M16 4 Meg x 16 x 4 banks 
Plastic Package (OCPL)    
66-pin TSOP TG 400 mil width, 0.65mm pin pitch
Timing (Cycle Time)     
7.5ns @ CL = 2 (DDR266B) -75Z
Supports PC2100 modules with 2-3-3 timing
7.5ns @ CL = 2.5 (DDR266B) -75
Supports PC2100 modules with 2.5-3-3 timing
10ns @ CL = 2 (DDR200) -8 Supports PC1600 modules with 2-2-2 timing
Self Refresh    
Standard None  
Low-Power L   
x16 IOL / IOH Drive    
Full Drive Only D1  
Reduced Drive Only D2  

 

256Mb: x4, x8, x16 DDR333 SDRAM Addendum

Part Features

  • 167 MHz Clock, 333 MHz data rate
  • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
  • Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte)
  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
  • Differential clock inputs (CK and CK#)
  • Commands entered on each positive CK edge
  • DQS edge-aligned with data for READs; center-aligned with data for WRITEs
  • DLL to align DQ and DQS transitions with CK
  • Four internal banks for concurrent operation
  • Data mask (DM) for masking write data (x16 has two - one per byte)
  • Programmable burst lengths: 2, 4, or 8
  • Concurrent Auto Precharge option supported
  • Auto Refresh and Self Refresh Modes
  • FBGA package available
  • 2.5V I/O (SSTL_2 compatible)
  • tRAS lockout ( tRAP = tRCD)
  • Backwards compatible with DDR200 and DDR266
Options Marking Notes
Configuration    
64 Meg x 4 64M4 16 Meg x 4 x 4 banks
32 Meg x 8 8M8 8 Meg x 8 x 4 banks
16 Meg x 16 16M16 4 Meg x 16 x 4 banks
Plastic Package    
66-Ball TSOP (OCPL) TG  
60-Ball FBGA FJ 16 x 8mm
Timing - Cycle Time    
6ns @ CL = 2.5 (DDR333B) -6 Supports PC2700 modules with 2.5-3-3 timing; only available in FBGA package
6ns @ CL = 3 -6T Supports PC2700 modules with 3-3-3 timing; only available in TSOP package
7.5ns @ CL = 2 (DDR266A) -75Z Supports PC2100 modules with 2-3-3 timing
7.5ns @ CL = 2.5 (DDR266B) -75 Supports PC2100 modules with 2.5-3-3 timing

 

512Mb: x4, x8, x16 DDR SDRAM

Part Features

  • •VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
  • Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte)
  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
  • Differential clock inputs (CK and CK#)
  • Commands entered on each positive CK edge
  • DQS edge-aligned with data for READs; center-aligned with data for WRITEs
  • DLL to align DQ and DQS transitions with CK
  • Four internal banks for concurrent operation
  • Data mask (DM) for masking write data (x16 has two – one per byte)
  • Programmable burst lengths: 2, 4, or 8
  • x16 has programmable IOL/IOV.
  • Concurrent auto precharge option is supported
  • Auto Refresh and Self Refresh Modes
  • Longer lead TSOP for improved reliability (OCPL)
  • 2.5V I/O (SSTL_2 compatible)

Part Options

Options Marking Notes
Configurations    
128 Meg x 4 128M4 32 Meg x 4 x 4 banks
64 Meg x 8 64M8 16 Meg x 8 x 4 banks
32 Meg x 16 32M16 8 Meg x 16 x 4 banks
Plastic Package (OCPL)    
66-pin TSOP TG 400 mil width, 0.65mm pin pitch
Timing (Cycle Time)    
7.5ns @ CL = 2 (DDR266B) -75Z
Supports PC2100 modules with 2-3-3 timing
7.5ns @ CL = 2.5 (DDR266B) -75
Supports PC2100 modules with 2.5-3-3 timing
10ns @ CL = 2 (DDR200) -8 Supports PC1600 modules with 2-2-2 timing
Self Refresh    
Standard None  
Low-Power L  


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